The phase noise characteristics of a signal generated by a Phase Locked Loop (PLL) circuit are used as an index indicating the purity of the signal. The phase noise of the PLL circuit is the characteristic that influences the performance of the radio apparatus using the PLL circuit therein, so that the phase noise of the PLL circuit is an important performance index for the PLL circuit.
The PLL circuit generally includes a phase comparator, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. The frequency divider divides the frequency of the oscillation signal output from the VCO into 1/N frequency, and outputs the divided signal (frequency divided signal). The phase comparator compares the phases between the reference signal from the reference oscillator and the divided signal, and outputs the signal indicating the phase comparison result. The loop filter integrates the signal indicating the phase comparison result, and supplies a voltage signal having a voltage level corresponding to the integration result to the VCO. The VCO oscillates at the frequency based on the voltage signal. In the case where the frequency difference between the reference signal and the divided signal becomes zero when the VCO oscillates based on the voltage signal generated by the loop filter, the voltage of the voltage signal converges to a constant voltage and the PLL circuit is in a locked state.
References are made to Japanese Laid-open Patent Publication Nos. 05-308283 and 2011-119903.